- feeds
- popular
- recent
- reader
- about
- story
- technologies
- what is rss
- connect
- dmca
- contact
- Feed Preview Cadence IC Packaging and SiP Design Forum
How to avoid adding degassing holes to a particular shape
In a package design, designers often need to perform degassing. This is typically done at the end of the design process before sending the design to the manufacturer. Degassing is a process whe...
DFA check space of compont to BGA ball or BGA PAD in APD
Hi， There are mang components in BGA ball side of flipchip package. Are there DFA check space of compont body or pin soldermask to BGA ball or BGA PAD or bga soldermask in allegro APD? ...
Find Routing problem (Route Vision) and quickly to fix these problems
The vision manager is good tool for routing check. but no quickly or effective tool to fix or optimize this problems to be optimized. For example, parallel Gap less than preferred, min seg...
modify bump and export the modified bump
hello, help me! There are many change in the bump design. I want to design bump by APD. The bump(die) is a stagger , create it by die generator. Because，the pin is not isometric. In or...
Allegro: Tip of the Week : Push Connectivity
At times, there might arise a condition in the design where you need to push the net of selected pins to all its physically connected objects. For example, a few pins are updated with a new net,...
Skill to delete selected net and padstakck via
Hi， I want to delete via use skill，but i dont write this skill. can you help me. This skill has Interactive interface，the interface can imput Select Net and select padstack； I can...
How to export and import symbols and component properties through Die Text wizards
Starting SPB 23.1, Allegro X APD lets you import/export the symbol and component properties by using DIE TEXT-IN/OUT wizards. EXPORTING THE SYMBOL You can export the symbol by using FILE ...
How to access the Transmission Line Calculator in Allegro X APD
Have you ever thought of a handy utility to specify all necessary transmission line parameters to decide upon the stackup? Starting SPB 23.1, a handy feature TRANSMISSION LINE CALCULATOR,...
How to add wirebond profile to a die pin?
Starting SPB 23.1, a new pin property, WIREBOND_PROFILE_NAME is introduced. This property can be used to define a wirebond profile to a die pin. When adding a wirebond, the pin will use the pr...
How to allow DRCs to the surrounding objects using Etch Back option
Starting from SPB23.1, a new option, ALLOW DRCS TO SURROUNDING METAL, has been added in the ETCH-BACK form to allow DRCs to the surrounding objects. form to allow DRCs to the surrounding o...
How to reuse device files for existing components
Have you ever encountered ERROR(SPMHNI-67) while importing logic? If yes, you might already know that you had to export libraries of the design and make sure that paths (devpath, padpath, and psm...
Introducing new 3DX Canvas in Allegro X Advanced Package Designer
Have you heard that starting SPB 23.1, Allegro Package Designer Plus (APD+) will be renamed as ALLEGRO X ADVANCED PACKAGE DESIGNER (Allegro X APD)? Allegro X APD offers multiple new fea...
What is Allegro X Advanced Package Designer and why do I not see Allegro Package Designer Plus (APD+) in 23.1?
Starting SPB 23.1, Allegro Package Designer Plus (APD+) has been rebranded as Allegro X Advanced Package Designer (Allegro X APD). The splash screen for ALLEGRO X APD will appear as shown�...
Aligning Components using Offset Mode in Allegro X APD
Starting SPB 23.1, in Allegro X PCB Editor and Allegro X Advanced Package Designer, you can align components by using offset mode. Earlier only spacing mode was available. Follow these steps to...
Multiple touch points for bond wires on a die pin
Does anyone know whether it is possible to have multiple contact points for a bond wire on a large die pad? Note: This is different from adding multiple wires which I will also be doing. I need t...
Relative delay analysis is impacted by pbar
Does anyone know how to not include a pbar in a constraint manager analysis? I have some relative delay constraints applied on a group of differential nets. When I analyze the design these all sh...
Allegro X APD: SPB 23.1 release —Your freedom to design boldly!
Cadence is super excited to announce SPB 23.1 RELEASE —YOUR FREEDOM TO DESIGN BOLDLY! These tools help engineers build better PCBs faster with the new 3D engine and optimized interface. ...
Does anyone know how to connect two pins of a die to the same net so they are considered a short inside of APD?
I'm trying to create a specific use case that has a die component with both topside and backside connections. The catch is that these connections need to be considered an electrical short. When ...
Vias are gone in 3D Cavas
All vias are not displayed in 3D canvas whereas they are shown in 3D. The design layout is made by Allegro Package Designer+. This is 4-layer(1-2-1) design, and each padstack is defined as "mic...
Extracting Parasitic RLC on Cadence APD+
Hi Just want to have your comment or maybe help me understand if the Cadence APD+ can extract accurately the parasitic RLC of the layout? And if yes, what parameters or settings should be obser...
APD+ 22.1 on Linux Environment Abnormal Display
My company is using APD+ on a Linux platform and I have encountered some display concerns as the following: 1. Whenever I hover my mouse over a via, it abnormally zooms in (my screen becomes t...
How to check same net spacing for microvias
I tried using the Check Same Net Spacing: Micovia To Microvia method. However, it generated too many errors that I couldn't distinguish between "OK" and "Not Good," as example picture. Has anyone...
how to convert .pcb format file to .mcm for apd+ v22
How do i import a xpedition layout .pcb file to cadence apd+
Varying height properties for single footprint
Version: Orcad 17.4 Licenses: Capture & CIS, EDM, CIP, PCB Editor professional We currnetly use CIP to manage part information with EDM managed projects, symbols and footprints. Most of th...
Where i can find sample IC package design file ?
Hi Team, I am new in IC package design. I need sample design for IC package . is any one let me know where i can get . Sample design in C Drive path ?