Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
As first silicon success declines, new software aims to provide a more holistic view of coverage data from multiple sources.
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circui...
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.
The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.
New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.