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Imperas and Synopsys team on RISC-V debug
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
https://www.techdesignforums.com/blog/2023/02/28/imperas-synopsys-integration-risc-v/
Siemens harnesses machine learning for more comprehensive verification
As first silicon success declines, new software aims to provide a more holistic view of coverage data from multiple sources.
Accellera forms CDC working group and takes security standard to IEEE
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
https://www.techdesignforums.com/blog/2023/01/18/accellera-cdc-working-group-ieee-security/
DVCon Europe best paper speeds up memory-controller tests
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circui...
https://www.techdesignforums.com/blog/2023/01/06/dvcon-europe-best-paper-memory-tests/
A*Star lays out SiP applications choices at IEDM
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
https://www.techdesignforums.com/blog/2023/01/04/astar-iedm-heterogeneous-integration/
RISC-V gets verification and security IP additions
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
https://www.techdesignforums.com/blog/2022/12/12/risc-v-imperas-codasip-summit/
Imec adds MOL layer to potentially cut cell size 20%
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
https://www.techdesignforums.com/blog/2022/12/09/imec-mol-vhv-4t-cell-iedm/
Imec pushes endurance on ferro memory at IEDM
Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.
https://www.techdesignforums.com/blog/2022/12/05/imec-endurance-ferroelectric-memory-iedm/
Identifying AI opportunities in PCB design
The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.
https://www.techdesignforums.com/blog/2022/12/01/ai-opportunities-in-pcb-design/
Siemens aims to simplify compliance for Linux medical devices
New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.