Plasma induced damage (PID) in gate oxide is a threat to MOSFET circuit yield and reliability. How can you effectively combat this issue?
A comprehensive guide to parasitics, how to perform parasitic extraction and the latest technologies available for this critical task.
RISC-V adoption is growing fast as is the ecosystem around the open-source core. Hardware and software are now vital for appropriate debug.
https://www.techdesignforums.com/practice/technique/debugging-complex-risc-v-processors/
TCP-Net is Test Case Prioritization using End-to-End Deep Neural Networks and addresses the challenges of today's software-rich projects.
Learn which routing techniques offer a PCB designer the best balance between automation and control by applying them in harmony.
https://www.techdesignforums.com/practice/technique/mastering-the-art-of-pcb-routing/
How the latest DFT techniques pave the way for quality and success for today's advanced designs.
https://www.techdesignforums.com/practice/technique/the-keys-to-ensuring-ic-quality/
Take a high level view of the AI strategies used within the Tessent family to improve across-the-board performance.
https://www.techdesignforums.com/practice/technique/tessent-ai-test-strategy/
A deep dive into the adoption, selection and implementation of models that boost productivity and customer loyalty.
The Boundary Condition Independent Reduced Order Model (BCI-ROM) provides vital help in addressing growing electro-thermal challenges in SPICE simulation.
Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.