Signal Processing Design

Increasingly, DSPs and FPGAs are being used together to solve consumer “triple play” multimedia applications. We not only cover technology from the systems angle, but also from the IC design and development tools side as well.

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Save Time and Improve Productivity with the digiVIT Advanced Digital Signal Conditioner from Kaman

Wed August 16th, 2017

User-friendly interface offers easier setup and connectivity along with cloud-based data access

http://signal-processing.mil-embedded.com/news/save-digital-signal-conditioner-kaman/

Technology Submission – Featured Project Development – ...rbine RotaryTurbo, 2-Imploturbocompressor One Compression Step

Sat August 12th, 2017

*State of the Art Novel InFlowTech; *1-Gearturbine-RotaryTurbo-Similar to Aeolipile 10-70 AD-Retrodynamic = Dextro RPM VS Levo InFlow + YingYang Way Power Type-Non Waste Looses / *2-Imploturbocom...

http://signal-processing.mil-embedded.com/news/technology-one-compression-step/

Vislink Receives $200,000 In Orders For Microwave Communications Equipment

Thu August 10th, 2017

African Police Force Using Technology for Airborne Surveillance

http://signal-processing.mil-embedded.com/news/vislink-200000-orders-microwave-communications-equipment/

LinkedHope Released A 6U VPX Computing Payload Based on Intel Xeon-D Processor

Fri August 4th, 2017

August 4th, 2017, as an independent embedded computer manufacturer, LinkedHope launched a China local-designed, local-manufactured 6U VPX board, named VP62107.

http://signal-processing.mil-embedded.com/news/linkedhope-based-intel-xeon-d-processor/

OneSpin’s Formal Verification Verifies Solutions to Einstein’s Riddle

Thu July 27th, 2017

Winning Entry from Nokia's Wolfgang Roessel, Runners Up from Infineon, ARM

http://signal-processing.mil-embedded.com/news/onespins-verifies-solutions-einsteins-riddle/

TEWS TECHNOLOGIES Adds New User-Programmable FPGA Module to Expanding Line of XMCs

Wed July 19th, 2017

TEWS TECHNOLOGIES increases its I/O offering with the TXMC638, a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable Kintex-7 FPGA with 24 ADC inpu...

http://signal-processing.mil-embedded.com/news/tews-fpga-module-expanding-line-xmcs/

Saelig Introduces PicoVNA 106 Low-Cost Vector Network Analyzer

Mon July 17th, 2017

Economical USB-controlled, professional-grade 300 kHz to 6 GHz Vector Network Analyzer with excellent performance, portability, and affordability.

http://signal-processing.mil-embedded.com/news/saelig-vector-network-analyzer/

OneSpin Solutions Showcases Innovative Formal Verification Solutions at DAC

Tue June 13th, 2017

DAC Program Features OneSpin Experts, including Raik Brinkmann on AI, Neural Networks Panel Moderated by Jim Hogan

http://signal-processing.mil-embedded.com/news/onespin-formal-verification-solutions-dac/

Verific Acquires INVIO Platform from Invionics Software

Mon June 12th, 2017

Rapid Application Development Platform will be added to Verific's Parser Platform

http://signal-processing.mil-embedded.com/news/verific-invio-platform-invionics-software/

FPGA designers turn to machine learning in the cloud

Fri June 9th, 2017

Even with all the attention focused on mobile-device apps for everything from ride sharing and Instagram to music streaming, the semiconductor industry still holds sway for passionate engineers w...

http://signal-processing.mil-embedded.com/guest-blogs/fpga-turn-machine-learning-the-cloud/

Spectrum’s AWGs tackle cost effective multi-channel signal generation and offer up to 24 fully synchronous channels

Fri June 9th, 2017

Spectrum's DN6.66xx series of AWGs offers up to 24 fully synchronized channels for applications such as MIMO, radar, quantum computing and multi-lane serial bus testing.

http://signal-processing.mil-embedded.com/news/spectrums-generation-offer-to-fully-synchronous-channels/

MEDIA ALERT: Oski Technology DAC Demonstrations to Showcase...VIP Library for AMBA Interface Protocols, Oski Formal Sign-Off

Thu June 8th, 2017

"New Frontiers in Formal Verification" Design/EDA Track Session Will Include Oski, ArterisIP Presentation "Architectural Formal Verification of Cache Coherent Protocols"

http://signal-processing.mil-embedded.com/news/media-oski-formal-sign-off/